Epson SED 1520 Series User Manual download pdf (Page 13)

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S-MOS SYSTEMS, INC.

2.0 – 2.3 2.0 Pin Description

2.0 Pin Description

2.1 Power Signals

• VDD

Connected to +5V power. Common to MPU

power pin V

CC.

• V

SS

0V, connected to system GND.

• V1 – V5

Multi-level power used to drive LCDs. Voltage

specified to each LCD cell is divided by resis-

tors or impedance-converted by an operational

amplifier before being applied. Each voltage to

be applied must be based on V

DD, while fulfill-

ing the following conditions:

V

DD ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ V5

2.2 System Bus Interface Signals

• D7 – D0

8-bit, tri-state, bi-directional I/O bus. Normally,

connected to the data bus of an 8-/16-bit stan-

dard microcomputer.

•A0

Input pin. Normally, the LSB of the MPU ad-

dress bus is connected to this input pin to

provide data/command selection.

0 : Display control data on D0 — D7

1 : Display data on D0 — D7

• RES

Input pin. The SED1520 can be reset or initial-

ized by setting RES to low level (if it is inter-

faced with a 68-family MPU) or high level (if

with an 80-family MPU). This reset operation

occurs when an edge of the RES signal is

sensed. The level input selects the type of

interface with the 68- or 80-family MPU:

High level : Interface with 68-family MPU

Low level : Interface with 80-family MPU

•CS

Chip Select input signal which is normally

obtained by decoding an address bus signal.

Effective with “L” active and a chip operating

with external clocks. For a chip containing an

oscillator, CS works as an oscillation amplifier

input pin to which an oscillation resistor (R

f) is

connected. In this case, RD, WR and E must be

a signal ANDed with CS.

• E (RD)

• Chip interfaced with 68-family MPU:

Enable Clock signal input for the 68-

family MPU.

• Chip interfaced with 80-family MPU:

“L” active input pin to which the 80-family

MPU RD signal is connected. With this

signal held at “L”, the SED1520 data bus

works as output.

• R/W (WR)

• Chip interface with 68-family MPU:

Read/write control signal input pin.

R/W = “H” : Read

R/W = “L” : Write

• Chip interfaced with 80-family MPU:

“L” active input pin to which the 80-family

WR is connected. The signal on the data

bus is fetched by the leading edge of WR.

2.3 LCD Drive Circuit Signals

•CL

Input signal effective with a chip using external

clocks. This display data latch signal incre-

ments the line counter (at the trailing edge) or

the common counter (at the leading edge). CL

is connected to CL2 of the common driver. For

a chip containing an oscillator, this pin works as

the oscillation amplifier output pin to which an

oscillation resistor (R

f) is connected.

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