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S-MOS SYSTEMS, INC.
5.0 Electrical Characteristics 5.3.3
5.3.3 Display Control Timing
Input Timing
Ta = –20 to 75°C, VSS = –5.0V ±10%
Parameter Symbol Signal Condition Min Typ Max Unit
Low level pulse width t
WLCL 35 — — µs
High level pulse width t
WHCL
CL
35 — — µs
Rise time t
r — 30 150 ns
Fall time t
f — 30 150 ns
FR delay time t
DFR FR –2.0 0.2 2.0 µs
Output Timing
T
a
= –20 to 75°C, V
SS
= –5.0V ±10%
Parameter Symbol Signal Condition Min Typ Max Unit
FR delay time t
DFR FR CL = 100 pF — 0.2 0.4 µs
*1. The listed FR input delay time applies to the SED1521 and 1520 (slave).
The listed FR output delay time applies to the SED1520 (master).
*2. Each of the values where V
SS = –3.0V is about 200% of that where VSS = –5.0V (i.e., the listed value).
t
WLCL
t
WHCL
t
DFR
t
f
t
r
CL
FR
Figure 5.7. Display control timing
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