Epson S1D13705 User Manual Page 179
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S1D13705 Register Summary X27A-R-001-03
Page 1 01/02/13
Notes
1 These bits are used to identify the S1D13705 at power on / reset.
2 IO addresses are relative to the beginning of display memory.
3 Gray Shade/Color Mode Selection
4 Panel Data Format
5 High Performance Selection
6 Power Save Mode Selection
REG[00h] REVISION CODE REGISTER
1
IO address = 1FFE0h
2
, RO
Product Code = 001001 Revision Code = 00
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 1 Bit 0
REG[01h] MODE REGISTER 0 IO address = 1FFE1h, RW
TFT/STN Dual/Single Color/Mono
3
FPLine
Polarity
FPFrame
Polarity
Mask
FPSHIFT
Data Width
4
Bit 1 Bit 0
REG[02h] MODE REGISTER 1 IO address = 1FFE2h, RW
Bit-Per-Pixel
3
High
5
Performance
Input Clock
Div (CLKI/2)
Display
Blank
Frame
Repeat
Hw Video
Invert
Enable
Software
Video Invert
Bit 1 Bit 0
REG[03h] MODE REGISTER 2 IO address = 1FFE3h, RW
n/a n/a n/a n/a
LCDPWR
Override
Hardware
PS Enable
Sw Power Save
6
Bit 1 Bit 0
REG[04h] HORIZONTAL PANEL SIZE REGISTER IO address = 1FFE4h, RW
n/a
Horizontal Panel Size = 8(REG + 1)
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
REG[05h] VERTICAL PANEL SIZE REGISTER (LSB) IO address = 1FFE5h, RW
Vertical Panel Size = (REG[05h], REG[06h]) + 1
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
REG[06h] VERTICAL PANEL SIZE REGISTER (MSB) IO address = 1FFE6h, RW
n/a n/a n/a n/a n/a n/a
Vertical Panel Size
Bit 9 Bit 8
REG[07h] FPLINE START POSITION IO address = 1FFE7h, RW
n/a n/a n/a
FPLine Start Position = 8(REG[07h] + 2)
Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
REG[08h] HORIZONTAL NON-DISPLAY PERIOD IO address = 1FFE8h, RW
n/a n/a n/a
Horizontal Non-Display Period = 8(REG + 4)
Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
REG[09h] FPFRAME START POSITION IO address = 1FFE9h, RW
n/a n/a
FPFrame Start Position
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
REG[0Ah] VERTICAL NON-DISPLAY PERIOD REGISTER IO address = 1FFEAh, RW
Vert Non-
Disp Status
n/a
Vertical Non-Display Period
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
REG[0Bh] MOD RATE REGISTER IO address = 1FFEBh, RW
n/a n/a
MOD Rate
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
REG[0Ch] SCREEN 1 START WORD ADDRESS REGISTER (LSB) IO address = 1FFECh, RW
Screen 1 Start Word Address = (REG[0Ch], REG[0Dh], REG[10] bit 1)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
REG[0Dh] SCREEN 1 START WORD ADDRESS REGISTER (MSB) IO address = 1FFEDh, RW
Screen 1 Start Word Address
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
REG[0Eh] SCREEN 2 START WORD ADDRESS REGISTER (LSB) IO address = 1FFEEh, RW
Screen 2 Start Word Address = (REG[0E], REG[0Fh], REG[10] bit 4)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
REG[0Fh] SCREEN 2 START WORD ADDRESS REGISTER (MSB) IO address = 1FFEFh, RW
Screen 2 Start Word Address
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
REG[10h] SCREEN START ADDRESS OVERFLOW REGISTER) IO address = 1FFF0h, RW
Screen 2
Start Add
Bit 16
Screen 1
Start Add
Bit 16
REG[11h] MEMORY ADDRESS OFFSET REGISTER IO address = 1FFF1h, RW
Memory Address Offset
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
REG[12h] SCREEN 1 VERTICAL SIZE REGISTER (LSB) IO address = 1FFF2h, RW
Screen 1 Vertical Size = (REG[12h], REG[13h])
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
REG[13h] SCREEN 1 VERTICAL SIZE REGISTER (MSB) IO address = 1FFF3h, RW
n/a n/a n/a n/a n/a n/a
Screen 1 Vertical Size
Bit 9 Bit 8
REG[15h] LOOK-UP TABLE ADDRESS REGISTER IO address = 1FFF5h, RW
Look-Up Table Address
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
REG[17h] LOOK-UP TABLE DATA REGISTER IO address = 1FFF7h, RW
Look-Up Table Data
n/a n/a n/a n/a
Bit 3 Bit 2 Bit 1 Bit 0
REG[18h] GPIO CONFIGURATION CONTROL REGISTER IO address = 1FFF8h, RW
n/a n/a n/a
GPIO4 Pin
IO Config
GPIO3 Pin
IO Config
GPIO2 Pin
IO Config
GPIO1 Pin
IO Config
GPIO0 Pin
IO Config
REG[19h] GPIO STATUS / CONTROL REGISTER IO address = 1FFF9h, RW
n/a n/a n/a
GPIO4 Pin
IO Status
GPIO3 Pin
IO Status
GPIO2 Pin
IO Status
GPIO1 Pin
IO Status
GPIO0 Pin
IO Status
REG[1Ah] SCRATCH PAD REGISTER IO address = 1FFFAh, RW
Scratch Pad Register
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
REG[1Bh] SWIVELVIEW MODE REGISTER IO address = 1FFFBh, RW
SwivelView
Mode En.
SwivelView
Mode Sel.
n/a n/a n/a reserved
SwivelView PCLK Select
Bit 1 Bit 0
REG[1Ch] LINE BYTE COUNT REGISTER IO address = 1FFFCh, RW
Line Byte Count
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Color/Mono
REG[01] bit 5
Bit-Per-Pixel Bit 1
REG[02] bit 7
Bit-Per-Pixel Bit 0
REG[02] bit 6
Display Mode
1
0
0 2 Colors 1 Bit-Per-Pixel
1 4 Colors 2 Bit-Per-Pixel
1
0 16 Colors 4 Bit-Per-Pixel
1 256 Colors 8 Bit-Per-Pixel
0
0
0 2 Gray Shade 1 Bit-Per-Pixel
1 4 Gray Shade 2 Bit-Per-Pixel
1
0 16 Gray Shade 4 Bit-Per-Pixel
1 reserved
TFT/STN
REG[01]
bit 7
Color/
Mono
REG[01]
bit 5
Dual/
Single
REG[01]
bit 6
Data
Width
Bit 1
REG[01]
bit 1
Data
Width
Bit 0
REG[01]
bit 0
Function
0
0
0
0
0 Mono Single 4-bit LCD
1 Mono Single 8-bit LCD
1
0reserved
1reserved
1
0
0reserved
1 Mono Dual 8-bit LCD
1
0reserved
1reserved
1
0
0
0 Color Single 4-bit LCD
1 Color Single 8-bit LCD Format 1
1
0reserved
1 Color Single 8-bit LCD Format 2
1
0
0reserved
1 Color Dual 8-bit LCD
1
0reserved
1reserved
1 don’t care
0 9 bit TFT Panel
1 12 bit TFT Panel
High Performance
Bit-Per-Pixel
Bit 1
REG[02] bit 7
Bit-Per-Pixel
Bit 0
REG[02] bit 6
Display Modes
0
0
0 MClk = PClk/8 1 bit-per-pixel
1 MClk = PClk/4 2 bit-per-pixel
1
0 MClk = PClk/2 4 bit-per-pixel
1 MClk = PClk 8 bit-per-pixel
1XX MClk = PClk
Power Save Bit 1 Power Save Bit 0 Mode
0 0 Power Save Mode 1
0 1 reserved
1 0 reserved
1 1 Normal Operation
S1D13705 Register Summary X27A-R-001-03
- S1D13705 1
- TECHNICAL MANUAL 1
- Customer Support Information 3
- GRAPHICS 5
- Vancouver Design Center 10
- List of Tables 11
- List of Figures 13
- 2 Features 16
- 2.4 Display Modes 17
- 2.5 Clock Source 17
- 2.6 Miscellaneous 17
- 2.7 Package 17
- 4 Functional Block Diagram 21
- 4.1.4 Look-Up Table 22
- 4.1.5 LCD Interface 22
- 4.1.6 Power Save 22
- 5.1 Pinout Diagram 23
- 5.2 Pin Description 24
- 5.2.2 LCD Interface 26
- 5.2.3 Clock Input 27
- 5.2.4 Miscellaneous 27
- 5.2.5 Power Supply 27
- 6 D.C. Characteristics 30
- 7 A.C. Characteristics 32
- Table 7-1: SH-4 Timing 33
- 7.1.2 SH-3 Interface Timing 34
- Table 7-2: SH-3 Bus Timing 35
- Figure 7-5: Generic #1 Timing 38
- Table 7-5: Generic #1 Timing 38
- Figure 7-6: Generic #2 Timing 39
- Table 7-6: Generic #2 Timing 39
- 7.2 Clock Input Requirements 40
- Clock Input Waveform 41
- 7.3 Display Interface 42
- 7.3.2 Power Down/Up Timing 43
- HDP HNDP 44
- 8 Registers 61
- REG[01h] bit 7 62
- REG[01h] bit 5 62
- REG[01h] bit 6 62
- REG[01h] bit 1 62
- REG[01h] bit 0 62
- REG[02h] bit 7 63
- REG[02h] bit 6 63
- REG[03h] bit 2 65
- REG[18h] bit 0 65
- REG[19h] bit 0 65
- Address = 1FFEAh Read/Write 68
- REG[0Bh] MOD Rate Register 68
- Address = 1FFEBh Read/Write 68
- Address = 1FFF5h Read/Write 71
- × BPP/16)) 71
- (REG[1Bh] bit 7) 73
- (REG[1Bh] bit 6) 73
- (REG[1Bh] bits [1:0] 74
- 9 Frame Rate Calculation 75
- 10 Display Data Formats 76
- 11.1 Monochrome Modes 77
- 11.2 Color Modes 79
- 2 Bit-per-pixel Color Mode 80
- 4 Bit-per-pixel Color Mode 81
- 8 Bit-per-pixel Color Mode 82
- 12 SwivelView™ 83
- 13 Power Save Modes 88
- REG[03h] bits [1:0] 90
- 13.6 Clock Requirements 91
- 14 Mechanical Data 92
- THIS PAGE LEFT BLANK 100
- 1 Introduction 101
- 2 Initialization 102
- 2.3 Frame Rate Calculation 103
- 3 Memory Models 106
- 4 Look-Up Table (LUT) 109
- 4.1 Look-Up Table Registers 110
- 4.2.1 Color Modes 111
- 2 bpp color 112
- 4 bpp color 113
- 8 bpp color 114
- 4.2.2 Gray Shade Modes 116
- 4 bpp gray shade 118
- 5 Advanced Techniques 119
- 5.1.1 Registers 120
- 5.1.2 Examples 120
- 5.2 Panning and Scrolling 121
- 5.2.1 Registers 122
- 5.2.2 Examples 123
- 5.3 Split Screen 125
- 5.3.1 Registers 126
- 5.3.2 Examples 128
- 6.1 LCD Power Sequencing 129
- 6.2 Registers 129
- 6.3 LCD Enable/Disable 130
- 7 Hardware Rotation 131
- 7.3 Alternate Portrait Mode 133
- 7.4 Registers 134
- 7.5 Limitations 136
- 7.6 Examples 137
- 8 Identifying the S1D13705 141
- 9.1 Introduction 142
- 9.3 Using the HAL library 143
- 9.4 API for 13705HAL 143
- 9.4.1 Initialization 145
- 9.4.2 General HAL Support 146
- , to the start of screen 1 150
- WORD *pWord) 152
- 9.4.5 Power Save 154
- 9.4.6 Drawing 155
- 9.4.7 LUT Manipulation 156
- 10 Sample Code 160
- OffsetBytes--; 168
- 10.3 Header Files 171
- Page 1 01/02/13 179
- Page 2 01/02/13 180
- Table of Contents 183
- 13705CFG 185
- Installation 186
- Decode Addresses 187
- Register Address 187
- Display Buffer Address 187
- Color Depth 189
- SwivelView Enable 189
- Alternative Mode 189
- Clocks Tab 190
- Panel Tab 192
- Panel Power Tab 196
- Registers Tab 197
- 13705CFG Menus 198
- Save As 199
- Configure Multiple 200
- Mode Number 201
- Comments 202
- Document No. X27A-B-002-02 203
- 13705SHOW 205
- PC Intel Platform 206
- Embedded Platform 206
- Program Messages 207
- 13705SPLT Display Utility 209
- 13705SPLT 211
- 13705SPLT Example 213
- 13705VIRT Display Utility 215
- 13705VIRT 217
- 13705VIRT Example 219
- 13705PLAY Diagnostic Utility 221
- 13705PLAY 223
- 13705PLAY Example 225
- Scripting 226
- Document No. X27A-B-006-03 229
- 13705BMP 231
- 13705PWR Power Save Utility 233
- 13705PWR 235
- PC Platform 236
- Example Driver Builds 242
- Configuration 249
- Mode File 250
- Linux Console Driver 265
- S1D13705 Linux Console Driver 268
- Linux Console Driver S1D13705 269
- Installation Guide 281
- Windows 2000 284
- Windows 98/ME 285
- Windows 95 OSR2 286
- Evaluation Board User Manual 289
- Table 2-3: Jumper Settings 297
- 3 LCD Interface Pin Mapping 298
- 6 Technical Description 302
- 6.2 ISA Bus Support 303
- 6.3 Non-ISA Bus Support 303
- 6.4 Decoding Logic 304
- 6.5 Clock Input Support 304
- 6.10 Power Save Modes 305
- 7 Parts List 307
- 8 Schematic Diagrams 308
- Board User Manual 313
- DIP Switch - SW1 321
- 3.2 Configuration Jumpers 323
- 4 CPU Interface 327
- CPU Bus Connector Pin Mapping 328
- 329
- 5 LCD Interface Pin Mapping 330
- 6.7 Power Save Modes 332
- 6.8 Clock Options 333
- 7 Software 334
- 8 References 335
- 9 Parts List 336
- 10 Schematics 338
- 11 Board Layout 343
- 12 Technical Support 344
- Resource Management Issues 357
- TMPR3912 Microprocessor 361
- 3.1 Host Bus Pin Connection 369
- 4.1 General Description 372
- 4.3 S1D13705 Configuration 373
- 5.1 Hardware Description 374
- TMPR3912 375
- 5.2 IT8368E Configuration 376
- 5.4 S1D13705 Configuration 377
- 6 Software 378
- 7 Technical Support 379
- Power Consumption 381
- 1 S1D13705 Power Consumption 383
- = 3.3V, IO V 384
- 2 Summary 385
- Family of Microprocessors 387
- 2 Interfacing to the MC68328 394
- 2.4.1 Hardware Description 398
- pin function with 401
- 3.1 The MC68EZ328 System Bus 402
- 3.2 Chip-Select Module 402
- 3.4.1 Hardware Description 405
- . Enable DTACK pin 407
- 4.1 The MC68VZ328 System Bus 408
- 4.2 Chip-Select Module 408
- 4.4.1 Hardware Description 412
- 5 Software 416
- 6 References 417
- Interfacing to the NEC 419
- VR4102/VR4111 Microprocessor 419
- 2.1.1 Overview 426
- System RESET 430
- 2.1 The PC Card System Bus 444
- 3 S1D13705 Bus Interface 446
- 15K pull-up 448
- 4.3 Register/Memory Mapping 449
- Microprocessor 453
- 2 Interfacing to the MPC821 460
- 2.3 Memory Controller Module 463
- 3.1 Host Bus Interface Modes 465
- 4.1 Hardware Description 467
- 4.5 Test Software 472
- 2 Interfacing to the MCF5307 484
- 2.1.3 Burst Cycles 485
- 2.2 Chip-Select Module 486
- PR31500/PR31700 Processor 495
- PR31500/PR31700 510
- 2 S1D13704/5 Bus Interface 522
- 3.1 Hardware Connections 524
- 4 CPU Module Description 526
- 4.3 LCD Controller 527
- 4.3.1 S1D13704 vs. S1D13705 527
- 4.3.2 LCDPWR Polarity 527
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