Epson S1D13705 User Manual download pdf (Page 302)

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Page 14 Epson Research and Development

Vancouver Design Center

S1D13705 S5U13705B00C Rev. 1.0 ISA Bus Evaluation Board User Manual

X27A-G-005-03 Issue Date: 01/02/13

6 Technical Description

6.1 Embedded Memory Support

The S1D13705 contains 80K bytes of embedded, 16-bit, SRAM used for the display buffer

and a 32 byte internal register set.

Since the S1D13705 does not distinguish between memory and register accesses, both the

80K byte display buffer and the 32 byte register set must be memory mapped into the host’s

memory space.

When using the S5U13705B00C board on an ISA bus system, the board can be configured

to map the S1D13705 to one of two memory blocks.

The SRAM start address is determined by a DIP switch setting. See Table 2-1: “Configu-

ration DIP Switch Settings,” on page 8.

1. When switch S1-5 is in the closed position, the S1D13705 is mapped into segments

0C0000h and 0D0000h.

This memory space is in the first 1M byte of ISA bus memory and should be used if

these segments are not taken up by other devices such as network adapters, SCSI

cards, or other peripherals.

Note

Since VGA and VGA compatible video adapters use address 0C8000, these cards can-

not be used while using the S5U13705B00C board at this memory address. A mono-

chrome display adapter, a terminal, or a non-VGA compatible display adapter must be

used.

2. When switch S1-5 is in the open position, the S1D13705 is mapped into the upper

megabyte of ISA bus memory, starting address of F00000h. To use this memory on an

ISA bus system, the system BIOS has to be configured to set a memory ‘hole’ starting

at this address. Some systems allow the user to configure the size of this hole and the

starting address of where it begins while others just allow a 1M byte hole at the top of

the 16M byte memory space. This memory hole is configured by entering the system

CMOS Setup Utility. This memory space should be used if segments 0Dh and 0Eh are

being used by other devices or if a VGA display adapter is needed.

Starting at the SRAM start address, the board design decodes a 128K byte segment accom-

modating both the 80K byte display buffer and the S1D13705 internal register set. The

S1D13705 registers are mapped into the upper 32 bytes of the 128K byte segment (1FFE0h

to 1FFFFh).

When using the S5U13705B00C board on a non-ISA bus system, system or external

decode logic must map the S1D13705 into an appropriate memory space.

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