Epson S1D13705 User Manual Page 333
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Vancouver Design Center
S5U13705B00C Rev. 2.0 Evaluation Board User Manual S1D13705
Issue Date: 2002/09/16 X27A-G-014-02
6.8 Clock Options
The input clock (CLKI) frequency can be up to 50MHz for the S1D13705 if the internal
divide-by-2 mode is set. If the clock divider is not used, the maximum CLKI frequency is
25MHz. There is no minimum input clock frequency.
A 6.0MHz oscillator (U2, socketed) is provided as the input clock source. However,
depending on the LCD resolution, desired frame rate and power consumption budget,
another clock frequency may be required.
A jumper, JP7 is provided to allow CLKI input to be the same as BCLK input, for systems
in which is desired to use only one clock signal for both BCLK and CLKI.
The bus clock (BCLK) is selectable and can be provided by a 50MHz oscillator (U7,
socketed) or the host CPU (for non-PCI host).
- S1D13705 1
- TECHNICAL MANUAL 1
- Customer Support Information 3
- GRAPHICS 5
- Vancouver Design Center 10
- List of Tables 11
- List of Figures 13
- 2 Features 16
- 2.4 Display Modes 17
- 2.5 Clock Source 17
- 2.6 Miscellaneous 17
- 2.7 Package 17
- 4 Functional Block Diagram 21
- 4.1.4 Look-Up Table 22
- 4.1.5 LCD Interface 22
- 4.1.6 Power Save 22
- 5.1 Pinout Diagram 23
- 5.2 Pin Description 24
- 5.2.2 LCD Interface 26
- 5.2.3 Clock Input 27
- 5.2.4 Miscellaneous 27
- 5.2.5 Power Supply 27
- 6 D.C. Characteristics 30
- 7 A.C. Characteristics 32
- Table 7-1: SH-4 Timing 33
- 7.1.2 SH-3 Interface Timing 34
- Table 7-2: SH-3 Bus Timing 35
- Figure 7-5: Generic #1 Timing 38
- Table 7-5: Generic #1 Timing 38
- Figure 7-6: Generic #2 Timing 39
- Table 7-6: Generic #2 Timing 39
- 7.2 Clock Input Requirements 40
- Clock Input Waveform 41
- 7.3 Display Interface 42
- 7.3.2 Power Down/Up Timing 43
- HDP HNDP 44
- 8 Registers 61
- REG[01h] bit 7 62
- REG[01h] bit 5 62
- REG[01h] bit 6 62
- REG[01h] bit 1 62
- REG[01h] bit 0 62
- REG[02h] bit 7 63
- REG[02h] bit 6 63
- REG[03h] bit 2 65
- REG[18h] bit 0 65
- REG[19h] bit 0 65
- Address = 1FFEAh Read/Write 68
- REG[0Bh] MOD Rate Register 68
- Address = 1FFEBh Read/Write 68
- Address = 1FFF5h Read/Write 71
- × BPP/16)) 71
- (REG[1Bh] bit 7) 73
- (REG[1Bh] bit 6) 73
- (REG[1Bh] bits [1:0] 74
- 9 Frame Rate Calculation 75
- 10 Display Data Formats 76
- 11.1 Monochrome Modes 77
- 11.2 Color Modes 79
- 2 Bit-per-pixel Color Mode 80
- 4 Bit-per-pixel Color Mode 81
- 8 Bit-per-pixel Color Mode 82
- 12 SwivelView™ 83
- 13 Power Save Modes 88
- REG[03h] bits [1:0] 90
- 13.6 Clock Requirements 91
- 14 Mechanical Data 92
- THIS PAGE LEFT BLANK 100
- 1 Introduction 101
- 2 Initialization 102
- 2.3 Frame Rate Calculation 103
- 3 Memory Models 106
- 4 Look-Up Table (LUT) 109
- 4.1 Look-Up Table Registers 110
- 4.2.1 Color Modes 111
- 2 bpp color 112
- 4 bpp color 113
- 8 bpp color 114
- 4.2.2 Gray Shade Modes 116
- 4 bpp gray shade 118
- 5 Advanced Techniques 119
- 5.1.1 Registers 120
- 5.1.2 Examples 120
- 5.2 Panning and Scrolling 121
- 5.2.1 Registers 122
- 5.2.2 Examples 123
- 5.3 Split Screen 125
- 5.3.1 Registers 126
- 5.3.2 Examples 128
- 6.1 LCD Power Sequencing 129
- 6.2 Registers 129
- 6.3 LCD Enable/Disable 130
- 7 Hardware Rotation 131
- 7.3 Alternate Portrait Mode 133
- 7.4 Registers 134
- 7.5 Limitations 136
- 7.6 Examples 137
- 8 Identifying the S1D13705 141
- 9.1 Introduction 142
- 9.3 Using the HAL library 143
- 9.4 API for 13705HAL 143
- 9.4.1 Initialization 145
- 9.4.2 General HAL Support 146
- , to the start of screen 1 150
- WORD *pWord) 152
- 9.4.5 Power Save 154
- 9.4.6 Drawing 155
- 9.4.7 LUT Manipulation 156
- 10 Sample Code 160
- OffsetBytes--; 168
- 10.3 Header Files 171
- Page 1 01/02/13 179
- Page 2 01/02/13 180
- Table of Contents 183
- 13705CFG 185
- Installation 186
- Decode Addresses 187
- Register Address 187
- Display Buffer Address 187
- Color Depth 189
- SwivelView Enable 189
- Alternative Mode 189
- Clocks Tab 190
- Panel Tab 192
- Panel Power Tab 196
- Registers Tab 197
- 13705CFG Menus 198
- Save As 199
- Configure Multiple 200
- Mode Number 201
- Comments 202
- Document No. X27A-B-002-02 203
- 13705SHOW 205
- PC Intel Platform 206
- Embedded Platform 206
- Program Messages 207
- 13705SPLT Display Utility 209
- 13705SPLT 211
- 13705SPLT Example 213
- 13705VIRT Display Utility 215
- 13705VIRT 217
- 13705VIRT Example 219
- 13705PLAY Diagnostic Utility 221
- 13705PLAY 223
- 13705PLAY Example 225
- Scripting 226
- Document No. X27A-B-006-03 229
- 13705BMP 231
- 13705PWR Power Save Utility 233
- 13705PWR 235
- PC Platform 236
- Example Driver Builds 242
- Configuration 249
- Mode File 250
- Linux Console Driver 265
- S1D13705 Linux Console Driver 268
- Linux Console Driver S1D13705 269
- Installation Guide 281
- Windows 2000 284
- Windows 98/ME 285
- Windows 95 OSR2 286
- Evaluation Board User Manual 289
- Table 2-3: Jumper Settings 297
- 3 LCD Interface Pin Mapping 298
- 6 Technical Description 302
- 6.2 ISA Bus Support 303
- 6.3 Non-ISA Bus Support 303
- 6.4 Decoding Logic 304
- 6.5 Clock Input Support 304
- 6.10 Power Save Modes 305
- 7 Parts List 307
- 8 Schematic Diagrams 308
- Board User Manual 313
- DIP Switch - SW1 321
- 3.2 Configuration Jumpers 323
- 4 CPU Interface 327
- CPU Bus Connector Pin Mapping 328
- 329
- 5 LCD Interface Pin Mapping 330
- 6.7 Power Save Modes 332
- 6.8 Clock Options 333
- 7 Software 334
- 8 References 335
- 9 Parts List 336
- 10 Schematics 338
- 11 Board Layout 343
- 12 Technical Support 344
- Resource Management Issues 357
- TMPR3912 Microprocessor 361
- 3.1 Host Bus Pin Connection 369
- 4.1 General Description 372
- 4.3 S1D13705 Configuration 373
- 5.1 Hardware Description 374
- TMPR3912 375
- 5.2 IT8368E Configuration 376
- 5.4 S1D13705 Configuration 377
- 6 Software 378
- 7 Technical Support 379
- Power Consumption 381
- 1 S1D13705 Power Consumption 383
- = 3.3V, IO V 384
- 2 Summary 385
- Family of Microprocessors 387
- 2 Interfacing to the MC68328 394
- 2.4.1 Hardware Description 398
- pin function with 401
- 3.1 The MC68EZ328 System Bus 402
- 3.2 Chip-Select Module 402
- 3.4.1 Hardware Description 405
- . Enable DTACK pin 407
- 4.1 The MC68VZ328 System Bus 408
- 4.2 Chip-Select Module 408
- 4.4.1 Hardware Description 412
- 5 Software 416
- 6 References 417
- Interfacing to the NEC 419
- VR4102/VR4111 Microprocessor 419
- 2.1.1 Overview 426
- System RESET 430
- 2.1 The PC Card System Bus 444
- 3 S1D13705 Bus Interface 446
- 15K pull-up 448
- 4.3 Register/Memory Mapping 449
- Microprocessor 453
- 2 Interfacing to the MPC821 460
- 2.3 Memory Controller Module 463
- 3.1 Host Bus Interface Modes 465
- 4.1 Hardware Description 467
- 4.5 Test Software 472
- 2 Interfacing to the MCF5307 484
- 2.1.3 Burst Cycles 485
- 2.2 Chip-Select Module 486
- PR31500/PR31700 Processor 495
- PR31500/PR31700 510
- 2 S1D13704/5 Bus Interface 522
- 3.1 Hardware Connections 524
- 4 CPU Module Description 526
- 4.3 LCD Controller 527
- 4.3.1 S1D13704 vs. S1D13705 527
- 4.3.2 LCDPWR Polarity 527
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