Epson S1C33 Specifications download pdf (Page 10)

1 Product Overview

EPSON

S1C33 ASIC DESIGN GUIDE

EMBEDDED ARRAY S1X50000 SERIES

(*) SNRC: Net list rule checker

Table 1.1 Work Involved in Each Step of S1C33ASIC Development

Development step Work involved

Specifications verification • Selection of C33 macros and modules used

• Fixing the specifications of the user logic

• Verifying the package and pin assignment

specifications

• Verifying the test design specifications

• Verifying the EPOD specifications

Development environment preparation • Design kit start-up (S1X50000

Series

and C33

design kit)

User logic design • Schematic capture, functional notation, logic

synthesis

• User logic simulation

Combined simulation • Chip level net list creation

• Chip level simulation program creation (C33

assembler code)

• Chip level simulation

Design rule check • SNRC(*)

Bulk signoff • Floorplan creation (macro layout, pin assignment)

Finalizing the bulk size

Pre-simulation • Pre-simulation

Test design • ATPG (user logic block)

P&R • Automatic placement and routing, CTS insertion

• Back annotation SDF creation

Post-simulation • Post-simulation

ROM code handling • Finalizing the internal ROM code

• ROM code data conversion

Metal signoff

Test production flow

Sample shipment, evaluation, switchover to

mass production

1 2 ... 5 6 7 8 9 10 11 12 13 14 15 ... 97 98

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Epson S1C33 Specifications Page 10