Epson S1C33 Specifications download pdf (Page 76)

5 Simulation

EPSON

S1C33 ASIC DESIGN GUIDE

EMBEDDED ARRAY SSL50000 SERIES

5.2 System Level Simulation

Figure 5.3 System Level Simulation

5.3 Test Pattern Creation

When the logic design is complete, the next step is test pattern creation. Test patterns are not only used

in simulation to verify operation of the circuit design, but are also used in product pre-shipment in-

spection.

An assembler-based evaluation

program is loaded into ROM.

Simple

assembler

ROM

C compiler

Assembler

Linker

C33 custom

microcontroller model

CC33 AS33

Personal computer

Workstation

RAM

Verilog simulator

ASIC

and

other

technol-

ogies

1 2 ... 71 72 73 74 75 76 77 78 79 80 81 ... 97 98

ASIC DESIGN GUIDE 1
Contents 5
Chapter 1 Product Overview 7
S1C33 ASIC DESIGN GUIDE 10
Continued on following page 11
1 Product Overview 12
2.1 Overview 13
2.2 Block Diagram 14
2 C33 Macro Specifications 15
2.3 C33 Macro Pins 16
2.4 Special Signals 21
2.5 Clock and Reset Signals 21
C33 MACRO 22
1) 3.3V single power source 24
2) 2.0V 24
2.6.3 DC Characteristics 26
2.6.4 Current Consumption 27
2) 2.0V single power source 28
3) Analog power current 28
■ Zero scale error 29
■ Full scale error 29
2.6.6 AC Characteristics 30
2.6.6.1 Symbol Description 31
2) 3.3V single power source 35
3) 2.0V single power source 35
SRAM read cycle 35
1) 3.3/5.0V dual power source 35
3) 2.0V single power source 38
2) 3.3V single power source 38
Input, Output and I/O port 42
P_A[23:0] signals 43
DRAM fast-page access cycle 46
EDO DRAM page access cycle 47
DRAM self-refresh cycle 47
Burst ROM read cycle 48
Clock signals 51
(wait cycle) 53
(last cycle) 53
(C1 only) 53
OSC1 crystal oscillation 55
OSC3 crystal oscillation 56
OSC3 ceramic oscillation 56
2.6.6.8 PLL Characteristics 57
Chapter 3 C33 Test Functions 58
3 C33 Test Functions 59
3.2.2 Test Mode 60
<APF Format Example> 61
$PATTERN 62
3.3.2 Test Mode 66
C33 Macros 68
Circuit Pins 69
4.3.4 Floorplan 69
User circuits 70
User circuit 72
Test circuit 72
C33 macro 72
4.5 Test Pattern Creation 73
Chapter 5 Simulation 74
Test bench creation script 75
5.2 System Level Simulation 76
5.3 Test Pattern Creation 76
5.4 Simulation Environment 77
5.5 Running a Simulation 78
5 Simulation 79
5.5.4 Test Bench Structure 80
Chapter 6 Board Development 85
6.1 Development Environment 85
6 Board Development 86
6.2 Evaluation Board Design 88
Chapter 7 Mounting 91
7 Mounting 92
(back of the chip) is V 93
K60 (AD0) 94
7.2 Others 95
Epson IS energy savings 97

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Epson S1C33 Specifications Page 76

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