Epson S1C33 Specifications download pdf (Page 78)

5 Simulation

EPSON

S1C33 ASIC DESIGN GUIDE

EMBEDDED ARRAY SSL50000 SERIES

The C33 macro net list consists of the hard macros, the soft macros, and the I/O cells used. The librar-

ies shown above include a sample that forms the S1C33208, which is a general-purpose model in the

C33 Series that uses the C33 macros. Seiko Epson provided hard macros are included in the megacell

library.

5.5 Running a Simulation

5.5.1 Preparing for Simulation

The following setup is required prior to executing a simulation.

1) Define the C33 environment variable to point to the install directory.

2) Set up your system so that the verilog command runs the Verilog simulator.

csh> verilog

VERILOG-XL 2.8

Valid host command options:

-f <filename> read host command arguments from file

3) Edit the environment setup file as required.

The file $C33/bin/SETUP performs the settings required in the C33 simulation envi-

ronment.

5.5.2 Sample Simulation Execution

The following procedure executes the sample simulation.

csh> cd $C33/sim/verilog/Sample/t0

csh> mv trc trc_back

csh> ./qa_sample.csh

The results of the simulation will be stored in the following directory. Compare the results here to the

backed up results in the trc_back directory.

$C33/sim/verilog/Sample/t0/trc/sample/... Output directory

sample_f10emux1.log: Log file

sample_f10emux1.tb: Test bench file

sample_f10emux1.trc: Trace output file

1 2 ... 73 74 75 76 77 78 79 80 81 82 83 ... 97 98

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Epson S1C33 Specifications Page 78