Epson S1C33 Specifications Page 80

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5 Simulation
74
EPSON
S1C33 ASIC DESIGN GUIDE
EMBEDDED ARRAY SSL50000 SERIES
Example 1) Normal simulation
csh> c33_sim.csh sample.asm trc=test1 tcyc=100 cycle=300
tb=abc.tb tb=def.tb
The file sample.asm is input and executed at 10 MHz (10 ns) for 300 cycles. The files
abc.tb and def.tb are added to the test bench. The output file is ./trc/sample/
test1.trc.
A directory with the same name as the ASM_file is created in the trc directory, and the
results of the Verilog simulation are stored in a file with the name specified with the trc=
option.
Example 2) Debug simulation
csh> debug_sample.csh
>>> verilog
debug
files
copied
to
directory
-->
./samplex_f10emux1
>>> edit test bench samplex_f10emux1.tb
>>> run verilog with following command
source $C33/bin/SETUP
cd samplex_f10emux1
verilog.boo samplex_f10emux1.tb
The debug_sample.csh file consists of the qa_sample.csh file with the debug option add-
ed. In this case, a directory with the same name as the ASM_file is created, and the files necessary
for simulation are set up. To execute a Verilog simulation, execute the Source of the SETUP file,
switch to the generated directory, and execute verilog.boo with the test bench as the argument.
5.5.4 Test Bench Structure
The test bench consists of the assembled test bench component files specified by the "tb=" and
"incl=" options to the c33_sim.csh script. Directories are searched in the following order to
find these files.
(1) The tb directory where the simulation is performed.
(2) The user shared test bench in $C33/sim/verilog/ENV/user_tb
(3) The C33 shared test bench in $C33/sim/verilog/ENV/c33_tb
If multiple files with the same name exist in two or more of the above directories, the first file found
by the search procedure will be used.
When c33_sim.csh generates a test bench, it uses the "//_
_" format (two forward slashes and
two underscores) in places where component files are used as test benches.
The locations of the files can be displayed easily by using grep to search for the test bench files.
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